High performance semiconductors devices are often packaged in expensive ceramic or metal packages for enhanced electrical performance. The use of such packages by a semiconductor manufacturer becomes cost prohibitive as the selling price of the device is driven down. Manufacturers would like to assemble high performance packages in less expensive plastic packages. However, large pin-counts typically associated with high performance devices are not easy to accommodate in a plastic package. Use of conventional single layer metal lead frames in high pin-count devices creates high inductance levels in signal and power supply paths, resulting in undesirable signal noise during simultaneous signal switching. Also, to handle the large currents used in high performance devices, a single layer metal lead frame requires a larger number of power and ground leads, and thus a larger number of power and ground pads on a die, to distribute the additional current. Increasing the number of leads and number of pads opposes a goal of semiconductor manufacturers which is to minimize device size. Furthermore, fine lead pitches associated with high lead count devices dictate that leads must terminate farther away from a die, making wire bonds long. The longer the wire bond lengths, the higher the inductance levels in the device.
To overcome the inductance and noise problems of high performance devices in plastic packages, conventional metal lead frames have been modified to include multiple metal layers. Such multilayer metal lead frames typically include either a power or a ground voltage plane on which a semiconductor die is mounted. The voltage plane is usually formed from conventional lead frame materials, such as copper, a copper alloy, an iron-nickel-cobalt alloy, or an iron-nickel alloy, and is attached to a more or less standard single layer lead frame. Attachment of the voltage plane to a single layer lead frame is often accomplished by using a non-conductive adhesive tape, but may also be done by welding a portion of the plane to one or more leads of the lead frame. While a multilayer lead frame having a full voltage plane is an improvement over conventional single layer lead frames in terms of electrical performance, a disadvantage with such lead frames is that a manufacturer is typically limited to having either a full power plane or a full ground plane, but not both. Furthermore, the additional layer of the lead frame increases the cost considerably.
Another known multilayer lead frame combines a first full voltage plane with a second partial voltage plane to improve electrical performance over the one-plane multilayer lead frame design discussed above. In this device, a full voltage plane is attached to a single layer lead frame in a manner similar to that described above. In addition, an annular voltage plane is attached to the top of the full voltage plane, for instance by a non-conductive adhesive tape. A semiconductor die is positioned in the central opening of the annular plane and is attached to the full plane. Power bond pads of the die are wire bonded to one of either the annular plane or the full plane, while ground pads are wire bonded to the remaining voltage plane. A semiconductor device utilizing a multilayer lead frame with one full voltage plane and one partial voltage plane has improved electrical performance over a device having only a single voltage plane. However, the cost of such a multilayer lead frame is much higher than a single layer lead frame due to more material usage and more complex processing. These multilayer lead frames can be on the order of three times the cost of single layer metal lead frames.
One known method of achieving lower lead inductance, while also lowering cost in comparison to a multilayer metal lead frame, utilizes a single layer metal lead frame having a thin, ground plane bonded to the lead frame either below the die paddle of the lead frame or bonded to the lead frame such that the ground plane serves as the die paddle. The ground plane is made of a metal layer adhesively bonded to an insulating tape, which in turn is adhesively bonded to the lead frame. The cost reduction over multilayer lead frames is realized in part because of the ease of attaching the tape to the lead frame as opposed to attaching an additional stamped or etched metal layer to the lead frame. While use of such tape has cost benefits, performance is only marginally improved because the voltage plane is not in a direct current path from the die to the lead.
As an alternative to using stamped or etched metal lead frames, some semiconductor manufacturers have employed TAB (tape automated bonding) lead flames. TAB tape lead frames include an insulating film which serves as a support carrier for etched copper metal leads. Multilayer metal TAB lead frames have been employed to improve electrical performance, wherein one metal layer is used to form the leads and another metal layer is used to form a reference voltage plane. The two overlying metal layers, separated by the insulating film, create a microstrip configuration for controlling signal impedance. A significant drawback of TAB technology is cost. Die fabrication costs are greatly increased due to a need to "bump" the bond pads of the die (or alternatively to "bump" the TAB leads). Also, the cost of TAB tapes generally are higher than stamped and etched metal lead frames.
Each of the above methods known in the prior art addresses the problem of switching noise and inductance, but fails to address other significant problems associated with packaging high performance devices in plastic. For instance, none of the above methods resolve the problem of high lead counts in general. To achieve high performance, high numbers of leads, especially power and ground leads, are necessary. As an example, some devices require as many as one voltage lead for every three signal leads in order to achieve the performance capability of the semiconductor die. In order to get large numbers of leads into a plastic package, the leads are made very long and very narrow, due to a need to fan out the tight spacing of bond pads on a die to a much coarser lead spacing at the external lead tips for bonding to a circuit board, resulting in rather large package outlines. Besides increasing package size, another problem of long, finely spaced leads is the need to maintain co-planarity for reliable wire bonding. Such fragile leads are easily damaged and displaced during handling to the point that wire bonding to the leads is difficult. A widespread technique to alleviate the problems associated with fine leads is the use of a mechanical lead support in the form of a polyimide tape. The polyimide tape is adhesively attached to a plurality of leads in a lead frame, surrounding the die receiving area. The polyimide tape is usually bonded to the leads by the lead frame manufacturer and is left in place through encapsulation. Thus the ring is part of a final plastic packaged semiconductor device.
As demonstrated above, the prior art techniques developed to overcome the problems of inductance and noise in high performance packages have done little to reduce the overall package size or address the problem of long, finely spaced leads in plastic packages. Similarly, techniques known to address the fragility of fine-pitch leads have done nothing to combat inductance and simultaneous switching noise of high performance semiconductor devices. Accordingly, there is a need for an improved high performance plastic package having low inductance, and further for such package to be minimal in size and have a low manufacturing cost.